Bus Interconnection Networks

In bus interconnection networks every bus provides a communication medium between a set of processors. These networks are modeled by hypergraphs where vertices represent the processors and edges represent the buses. We survey the results obtained on the construction methods that connect a large number of processors in a bus network with given maximum processor degree , maximum bus size r, and network diameter D. (In hypergraph terminology this problem is known as the ((; D; r)-hypergraph problem.) The problem for point-to-point networks (the case r = 2) has been extensively studied in the literature. As a result, several families of networks have been proposed. Some of these point-to-point networks can be used in the construction of bus networks. One approach is to consider the dual of the network. We survey some families of bus networks obtained in this manner. Another approach is to view the point-to-point networks as a special case of the bus networks and to generalize the known constructions to bus networks. We provide a summary of the tools developed in the theory of hypergraphs and directed hypergraphs to handle this approach.